A typical method for fabricating a field effect transistor is illustrated in FIGS. 1(a-b). As shown in FIGS. 1(a-b), a lightly doped N- epitaxial layer with a thickness of about 180 .mu.m is grown on a 600 .mu.m N+ substrate. Once the N- epitaxial layer is grown, the field effect transistor is formed using the N- epitaxial layer and the N+ substrate.
The problem with the method described above is that the practical limit for the thickness of the epitaxial layer is about 200 .mu.m thick and some recent power device applications need the epitaxial layer to be about 300 .mu.m thick. The thickness of the epitaxial layer is limited because it is expensive to make thicker, it is difficult to manufacture, and when the epitaxial layer is made thicker it is more likely to have problems with material quality, such as stacking faults, non-uniformity of thickness, and non-uniformity of resistivity. Accordingly, the above-described method is not useful for power device applications which need the epitaxial layer, which is being used as the "primary" device layer, to be about 300 .mu.m thick.
One solution to this problem has been the use of silicon-on-silicon bonded wafers to provide a thicker device layer, i.e. about 300 .mu.m thick, however the use of these bonded wafers poses other problems. Primarily, the problem with this solution is its cost because it requires the purchase of an additional substrate wafer which is expensive. Additionally, there are typically processing problems with forming the bonded interface between the silicon-on-silicon wafers which reduces the yield of useful bonded wafers. Accordingly, the silicon-on-silicon bonded wafers are not a satisfactory solution.